`include "defines.v"

module mem(
    input  wire                      reset,
	 input  wire[`RegisterAddressBus] wd_input,
	 input  wire                      wreg_input,
	 input  wire[`RegisterBus]        wdata_input,
	 input  wire[`RegisterBus]        hi_input,
	 input  wire[`RegisterBus] 		  lo_input,
	 input  wire[`RegisterBus]        hilo_we,
	 
	 output  reg[`RegisterBus]        hi_o,
	 output  reg[`RegisterBus] 		  lo_o,
	 output  reg[`RegisterBus]        hilo_we_o,

	 output reg[`RegisterAddressBus]  wd_output,
	 output reg                       wreg_output,
	 output reg[`RegisterBus]         wdata_output
);

    always @ (*) begin
	     if (reset == `ResetEnable) begin
		      wd_output <= `NOPRegisterAddress;
				wreg_output <= `WriteDisable;
				wdata_output <= `ZeroWord;
				hi_o <= `ZeroWord;
				lo_o<= `ZeroWord;
				hilo_we_o <= `WriteDisable;
		  end else begin
		      wd_output <= wd_input;
				wreg_output <= wreg_input;
				wdata_output <= wdata_input;
				hi_o <= hi_input;
				lo_o <= lo_input;
				hilo_we_o <= hilo_we; 
		  end
	 end

endmodule